74AHC00D Download

partno	mfr	description	Magnitude	download
74AHC00D	PHILIPS	Philips Semiconductors [Quad 2-input NAND gate]	77k

INTEGRATED CIRCUITS DATA SHEET 74AHC00; 74AHCT00 Quad 2-input NAND gate Product specification Supersedes data of 1998 Dec 09 File under Integrated Circuits, IC06 1999 Sep 23 Philips Semiconductors Product specification Quad 2-input NAND gate FEATURES ? ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V ? Balanced propagation delays ? All inputs have Schmitt-trigger actions ? Inputs accept voltages higher than VCC ? For AHC only: operates with CMOS input levels ? For AHCT only: operates with TTL input levels ? Specified from -40 to +85 and +125 ?C. DESCRIPTION The 74AHC/AHCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT00 provides the 2-input NAND function. CI CO CPD Note 1. H = HIGH voltage level; L = LOW voltage level. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 ?C; tr = tf 3.0 ns. FUNCTION TABLE See note 1. INPUT nA L L H H nB L H L H 74AHC00; 74AHCT00 OUTPUT nY H H H L TYPICAL SYMBOL tPHL/tPLH PARAMETER propagation delay nA, nB to nY input capacitance output capacitance power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 CONDITIONS AHC CL = 15 pF; VCC = 5 V 3.2 AHCT 3.3 3.0 4.0 7.0 ns pF pF pF UNIT VI = VCC or GND 3.0 4.0 7.0 Notes 1. CPD is used to determine the dynamic power dissipation (PD in ?W). PD = CPD ? VCC2 ? fi + (CL ? VCC2 ? fo) where: fi = input frequency in MHz; fo = output frequency in MHz; (CL ? VCC2 ? fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. PINNING PIN 1, 4, 9 and 12 2, 5, 10 and 13 3, 6, 8 and 11 7 14 SYMBOL 1A to 4A 1B to 4B 1Y to 4Y GND VCC DESCRIPTION data inputs data inputs data outputs ground (0 V) DC supply voltage 1999 Sep 23 2 Philips Semiconductors Product specification Quad 2-input NAND gate ORDERING INFORMATION OUTSIDE NORTH AMERICA 74AHC00D 74AHC00PW 74AHCT00D 74AHCT00PW 74AHC00; 74AHCT00 PACKAGES NORTH AMERICA PINS 74AHC00D 74AHC00PW DH 74AHCT00D 74AHCT00PW DH 14 14 14 14 PACKAGE SO TSSOP SO TSSOP MATERIAL plastic plastic plastic plastic CODE SOT108-1 SOT402-1 SOT108-1 SOT402-1 handbook, halfpage 1A 1B 1Y 2A 2B 2Y GND 1 2 3 4 5 6 7 MNA210 14 VCC 13 4B handbook, halfpage 12 4A A Y B MNA211 00 11 4Y 10 3B 9 8 3A 3Y Fig.1 Pin configuration. Fig.2 Logic diagram (one gate). handbook, halfpage handbook, halfpage 1 2 & 3 1 2 4 5 9 10 12 13 1A 1B 2A 2B 3A 3B 4A 4B 1Y 3 4 & 6 2Y 6 5 3Y 8 9 10 & 8 4Y 11 12 & 11 MNA212 13 MNA246 Fig.3 Functional diagram. Fig.4 IEC logic symbol. 1999 Sep 23 3 Philips Semiconductors Product specification Quad 2-input NAND gate RECOMMENDED OPERATING CONDITIONS 74AHC SYMBOL VCC VI VO Tamb PARAMETER DC supply voltage input voltage output voltage operating ambient temperature range see DC and AC characteristics per device VCC = 5 V ?0.5 V CONDITIONS MIN. 2.0 0 0 -40 -40 74AHC00; 74AHCT00 74AHCT UNIT TYP. MAX. 5.0 - - +25 +25 - - 5.5 5.5 VCC +85 V V V ?C TYP. MAX. MIN. 5.0 - - +25 +25 - - 5.5 5.5 VCC +85 4.5 0 0 -40 +125 -40 100 20 - - +125 ?C - 20 ns/V tr,tf (t/f) input rise and fall rates VCC = 3.3 V ?0.3 V - - LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC VI IIK IOK IO ICC Tstg PD Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO packages: above 70 ?C the value of PD derates linearly with 8 mW/K. For TSSOP packages: above 60 ?C the value of PD derates linearly with 5.5 mW/K. PARAMETER DC supply voltage input voltage range DC input diode current DC output diode current DC VCC or GND current storage temperature range power dissipation per package for temperature range: -40 to +125 ?C; note 2 VI < -0.5 V; note 1 VO < -0.5 V or VO > VCC + 0.5 V; note 1 CONDITIONS MIN. MAX. UNIT -0.5 -0.5 - - - - -65 - +7.0 +7.0 -20 ?20 ?25 ?75 500 V V mA mA mA mA mW DC output source or sink current -0.5 V < VO < VCC + 0.5 V +150 ?C 1999 Sep 23 4 Philips Semiconductors Product specification Quad 2-input NAND gate DC CHARACTERISTICS 74AHC00; 74AHCT00 74AHC family Over recommended operating conditions; voltage are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER VIH HIGH-level input voltage VCC (V) 2.0 3.0 5.5 VIL LOW-level input voltage 2.0 3.0 5.5 VOH HIGH-level output voltage; all outputs HIGH-level output voltage VI = VIH or VIL; IO = -50 ?A VI = VIH or VIL; IO = -4.0 mA VI = VIH or VIL; IO = -8.0 mA VOL LOW-level output voltage; all outputs LOW-level output voltage VI = VIH or VIL; IO = 50 ?A VI = VIH or VIL; IO = 4 mA VI = VIH or VIL; IO = 8 mA II IOZ ICC CI input leakage current 3-state output OFF current quiescent supply current input capacitance VI = VCC or GND 2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 3.0 4.5 5.5 MIN. 1.5 2.1 - - - 1.9 2.9 4.4 - - - - - 2.0 3.0 4.5 25 TYP. - - - 0.5 0.9 1.65 - - - - - 0.1 0.1 0.1 0.36 0.36 0.1 Tamb (?C) -40 to +85 - - 0.5 0.9 1.65 - - - -40 to +125 UNIT - - 0.5 0.9 1.65 - - - V V V MAX. MIN. MAX. MIN. MAX. 1.5 2.1 - - - 1.9 2.9 4.4 1.5 2.1 - - - 1.9 2.9 4.4 V 3.85 - 3.85 - 3.85 - 2.58 - 3.94 - - - - - - - - - - 0 0 0 - - - - - 3 2.48 - 3.8 - - - - - - - 0.1 0.1 0.1 0.44 0.44 1.0 ?2.5 20 10 2.40 - 3.70 - - - - - - - - - - 0.1 0.1 0.1 0.55 0.55 2.0 V V ?A VI = VIH or VIL; 5.5 VO = VCC or GND VI = VCC or GND; IO = 0 5.5 - ?0.25 - 2.0 10 - - ?10.0 ?A 40 10 ?A pF 1999 Sep 23 5 Philips Semiconductors Product specification Quad 2-input NAND gate 74AHC00; 74AHCT00 74AHCT family Over recommended operating conditions; voltage are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage; all outputs HIGH-level output voltage VOL LOW-level output voltage; all outputs LOW-level output voltage II IOZ input leakage current 3-state output OFF current VI = VIH or VIL; IO = -50 ?A VI = VIH or VIL; IO = -8.0 mA VI = VIH or VIL; IO = 50 ?A VI = VIH or VIL; IO = 8 mA VI = VIH or VIL VCC (V) - - 4.5 25 - 0.8 - Tamb (?C) -40 to +85 - 0.8 - -40 to +125 UNIT - 0.8 - MIN. TYP. MAX. MIN. MAX. MIN. MAX. 2.0 - 4.4 2.0 - 4.4 V V V 4.5 to 5.5 2.0 4.5 to 5.5 - 4.5 4.4 4.5 4.5 3.94 - - 0 - 0.1 3.8 - - 0.1 3.70 - - 0.1 V V 4.5 5.5 - - - - - - 0.36 0.1 - - 0.44 1.0 ?2.5 - - - 0.55 2.0 V ?A VI = VIH or VIL; 5.5 VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 VI = VCC or GND; 5.5 IO = 0 VI = VCC - 2.1 V other inputs at VCC or GND; IO = 0 ?0.25 - ?10.0 ?A ICC ICC quiescent supply current additional quiescent supply current per input pin input capacitance - - - 2.0 1.35 - - 20 1.5 - - 40 1.5 ?A mA 4.5 to 5.5 - CI - - 3 10 - 10 - 10 pF 1999 Sep 23 6 Philips Semiconductors Product specification Quad 2-input NAND gate AC CHARACTERISTICS Type 74AHC00 GND = 0 V; tr = tf 3.0 ns. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS VCC = 3.0 to 3.6 V; note 1 tPHL/tPLH propagation delay nA, nB to nY see Figs 5 and 6 15 pF - 50 pF - see Figs 5 and 6 15 pF - 50 pF - 4.5 6.0 7.9 11.4 CL MIN. 25 TYP. MAX. 74AHC00; 74AHCT00 Tamb (?C) -40 to +85 MIN. MAX. -40 to +125 MIN. MAX. UNIT 1.0 1.0 9.5 13.0 1.0 1.0 10.0 14.5 ns ns VCC = 4.5 to 5.5 V; note 2 tPHL/tPLH propagation delay nA, nB to nY 3.2 4.5 5.5 7.5 1.0 1.0 6.5 8.5 1.0 1.0 7.0 9.5 ns ns Notes 1. Typical values at VCC = 3.3 V. 2. Typical values at VCC = 5.0 V. Type 74AHCT00 GND = 0 V; tr = tf 3.0 ns. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS VCC = 4.5 to 5.5 V; note 1 tPHL/tPLH propagation delay nA, nB to nY see Figs 5 and 6 15 pF - 50 pF - 3.3 4.5 6.9 7.9 1.0 1.0 8.0 9.0 1.0 1.0 9.0 10.0 ns ns CL MIN. 25 TYP. Tamb (?C) -40 to +85 MAX. MIN. MAX. -40 to +125 MIN. MAX. UNIT Note 1. Typical values at VCC = 5.0 V. 1999 Sep 23 7 Philips Semiconductors Product specification Quad 2-input NAND gate AC WAVEFORMS 74AHC00; 74AHCT00 handbook, halfpage nA, nB INPUT VM(1) tPHL tPLH nY OUTPUT VM(1) MNA213 FAMILY 74AHC 74AHCT VI INPUT REQUIREMENTS GND to VCC GND to 3.0 V VM(1) INPUT 50% VCC 1.5 V VM(1) OUTPUT 50% VCC 50% VCC Fig.5 The input (nA) to output (nY) propagation delay. handbook, full pagewidth S1 VCC PULSE GENERATOR VI D.U.T. RT CL MNA219 VO 1000 VCC open GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH open VCC GND S1 Fig.6 Load circuitry for switching times. 1999 Sep 23 8 Philips Semiconductors Product specification Quad 2-input NAND gate PACKAGE OUTLINES SO14: plastic small outline package; 14 leads; body width 3.9 mm 74AHC00; 74AHCT00 SOT108-1 D E A X c y HE v M A Z 14 8 Q A2 A1 pin 1 index Lp 1 e bp 7 w M L detail X (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.050 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012 inches 0.069 0.010 0.057 0.004 0.049 0.019 0.0100 0.35 0.014 0.0075 0.34 0.244 0.039 0.041 0.228 0.016 8 0o o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06S JEDEC MS-012AB EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-23 97-05-22 1999 Sep 23 9 Philips Semiconductors Product specification Quad 2-input NAND gate 74AHC00; 74AHCT00 TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E A X c y HE v M A Z 14 8 Q A2 pin 1 index A1 Lp L (A 3) A 1 e bp 7 w M detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.10 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 8 0o o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 EIAJ EUROPEAN PROJECTION ISSUE DATE 94-07-12 95-04-04 1999 Sep 23 10 Philips Semiconductors Product specification Quad 2-input NAND gate SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 ?C. The top-surface temperature of the packages should preferable be kept below 230 ?C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: 74AHC00; 74AHCT00 ? Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? For packages with leads on two sides and a pitch (e): ? larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; ? smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. ? For packages with leads on four sides, the footprint must be placed at a 45? angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 ?C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 ?C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 ?C. 1999 Sep 23 11 Philips Semiconductors Product specification Quad 2-input NAND gate 74AHC00; 74AHCT00 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45? angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable suitable suitable suitable suitable suitable REFLOW(1) 1999 Sep 23 12 Philips Semiconductors Product specification Quad 2-input NAND gate NOTES 74AHC00; 74AHCT00 1999 Sep 23 13 Philips Semiconductors Product specification Quad 2-input NAND gate NOTES 74AHC00; 74AHCT00 1999 Sep 23 14 Philips Semiconductors Product specification Quad 2-input NAND gate NOTES 74AHC00; 74AHCT00 1999 Sep 23 15 Philips Semiconductors ? a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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