74ABT Download

partno	mfr	description	Magnitude	download
74ABT	NSC	National Semiconductor [Octal Transparent Latch with TRI-STATE Outputs]	342k

54ABT 74ABT373 Octal Transparent Latch with TRI-STATE Outputs September 1995 54ABT 74ABT373 Octal Transparent Latch with TRI-STATE Outputs General Description The 'ABT373 consists of eight latches with TRI-STATE outputs for bus organized system applications The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH When LE is LOW the data that meets the setup times is latched Data appears on the bus when the Output Enable (OE) is LOW When OE is HIGH the bus output is in the high impedance state Y Y Y Y Y Y Features Y Y Y Y TRI-STATE outputs for bus interfacing Output sink capability of 64 mA source capability of 32 mA Guaranteed output skew Guaranteed multiple output switching specifications Output switching specified for both 50 pF and 250 pF loads Guaranteed simultaneous switching noise level and dynamic threshold performance Guaranteed latchup protection High impedance glitch free bus loading during entire power up and power down Nondestructive hot insertion capability Standard Military Drawing (SMD) 5962-9321801 Commercial 74ABT373CSC (Note 1) 74ABT373CSJ (Note 1) 74ABT373CPC Military Package Number M20B M20D N20B Package Description 20-Lead (0 300 Wide) Molded Small Outline JEDEC 20-Lead (0 300 Wide) Molded Small Outline EIAJ 20-Lead (0 300 Wide) Molded Dual-In-Line 20-Lead Ceramic Dual-In-Line 20-Lead Molded Shrink Small Outline EIAJ Type II 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C 20-Lead Molded Thin Shrink Small Outline JEDEC 54ABT373J 883 74ABT373CMSA (Note 1) 54ABT373W 883 54ABT373E 883 74ABT373CMTC (Notes 1 2) Note 2 Contact factory for package availability J20A MSA20 W20A E20A MTC20 Note 1 Devices also available in 13 reel Use suffix e SCX SJX MSAX and MTCX Connection Diagrams Pin Assignment for DIP SOIC SSOP and Flatpak Pin Assignment for LCC Pin Names D0 ?D7 LE OE O0 ?O7 Description Data Inputs Latch Enable Input (Active HIGH) Output Enable Input (Active LOW) TRI-STATE Latch Outputs TL F 11547 ? 2 TL F 11547?1 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 11547 RRD-B30M115 Printed in U S A Functional Description The 'ABT373 contains eight D-type latches with TRI-STATE output buffers When the Latch Enable (LE) input is HIGH data on the Dn inputs enters the latches In this condition the latches are transparent i e a latch output will change state each time its D input changes When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE The TRI-STATE buffers are controlled by the Output Enable (OE) input When OE is LOW the buffers are in the bi-state mode When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches Truth Table Inputs LE H H L X OE L L L H Dn H L X X Output On H L On (no change) Z H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Z e High Impedance State Logic Diagram TL F 11547 ? 3 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays 2 Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic Plastic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) b 65 C to a 150 C b 55 C to a 125 C b 55 C to a 175 C b 55 C to a 150 C b 0 5V to a 7 0V b 0 5V to a 7 0V b 30 mA to a 5 0 mA b 150 mA DC Latchup Source Current OE Pin (Across Comm Operating Range) Other Pins b500 mA Over Voltage Latchup (I O) 10V Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not implied Note 2 Either voltage limit or current limit is sufficient to protect inputs Recommended Operating Conditions Free Air Ambient Temperature Military Commercial Supply Voltage Military Commercial Minimum Input Edge Rate Data Input Enable Input b 55 C to a 125 C b 40 C to a 85 C a 4 5V to a 5 5V a 4 5V to a 5 5V b 0 5V to a 5 5V b 0 5V to VCC twice the rated IOL (mA) (DV Dt) 50 mV ns 20 mV ns DC Electrical Characteristics Symbol VIH VIL VCD VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54ABT 74ABT 54ABT 74ABT 54ABT 74ABT 25 20 20 0 55 0 55 5 5 7 b5 b5 ABT373 Min 20 08 b1 2 Typ Max Units V V V V VCC Conditions Recognized HIGH Signal Recognized LOW Signal Min Min IIN e b18 mA IOH e b3 mA IOH e b24 mA IOH e b32 mA IOL e 48 mA IOL e 64 mA VIN e 2 7V (Note 2) VIN e VCC VIN e 7 0V VIN e 0 5V (Note 2) VIN e 0 0V IID e 1 9 mA All Other Pins Grounded VOL IIH IBVI IIL VID IOZH IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Input Leakage Test Output Leakage Current Output Leakage Current Output Short-Circuit Current Output High Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC Input V mA mA mA V Min Max Max Max 00 4 75 50 b 50 b 100 b 275 mA mA mA mA mA mA mA mA mA mA mA 0 b 5 5V VOUT e 2 7V OE e 2 0V 0 b 5 5V VOUT e 0 5V OE e 2 0V Max Max 00 Max Max Max VOUT e 0 0V VOUT e VCC VOUT e 5 5V All Others GND All Outputs HIGH All Outputs LOW OE e VCC All Others at VCC or GND VI e VCC b 2 1V Enable Input VI e VCC b 2 1V Data Input VI e VCC b 2 1V All Others at VCC or GND Outputs Open LE e VCC OE e GND (Note 1) One Bit Toggling 50% Duty Cycle 50 100 50 30 50 Outputs Enabled Outputs TRI-STATE Outputs TRI-STATE No Load 25 25 25 Max ICCD Dynamic ICC (Note 2) 0 12 mA MHz Max Note 1 For 8 bits toggling ICCD k 0 8 mA MHz Note 2 Guaranteed but not tested 3 DC Electrical Characteristics Symbol VOLP VOLV VOHV VIHD VILD Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL (SOIC Package) (Continued) Min Typ 04 b1 2 b0 8 Max 08 Units V V V V VCC 50 50 50 50 50 Conditions CL e 50 pF RL e 500X TA e 25 C (Note 1) TA e 25 C (Note 1) TA e 25 C (Note 3) TA e 25 C (Note 2) TA e 25 C (Note 2) Minimum High Level Dynamic Output Voltage Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage 25 20 30 17 09 06 V Note 1 Max number of outputs defined as (n) n b 1 data inputs are driven 0V to 3V One output at Low Guaranteed but not tested Note 2 Max number of data inputs (n) switching n b 1 inputs switching 0V to 3V Input-under-test switching 3V to theshold (VILD) 0V to threshold (VIHD) Guaranteed but not tested Note 3 Max number of outputs defined as (n) n b 1 data inputs are driven 0V to 3V One output HIGH Guaranteed but not tested AC Electrical Characteristics 74ABT Symbol Parameter TA e a 25 C VCC e a 5 0V CL e 50 pF Min tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Dn to On Propagation Delay LE to On Output Enable Time Output Disable Time 19 19 20 20 15 15 20 20 Typ 27 28 31 30 31 31 36 34 Max 45 45 50 50 53 53 54 54 54ABT TA e b55 C to a 125 C VCC e 4 5V to 5 5V CL e 50 pF Min 10 10 10 15 10 15 17 10 Max 68 70 77 77 67 72 80 70 74ABT TA e b40 C to a 85 C VCC e 4 5V to 5 5V CL e 50 pF Min 19 19 20 20 15 15 20 20 Max 45 45 50 50 53 53 54 54 ns ns ns ns Units AC Operating Requirements 74ABT Symbol Parameter Min ftoggle ts(H) ts(L) th(H) th(L) tw(H) Max Toggle Frequency Setup Time HIGH or LOW Dn to LE Hold Time HIGH or LOW Dn to LE Pulse Width LE HIGH 15 15 10 10 30 TA e a 25 C VCC e a 5 0V CL e 50 pF Typ 100 Max 54ABT TA e b55 C to a 125 C VCC e 4 5V to 5 5V CL e 50 pF Min 100 25 25 25 25 33 15 15 10 10 30 Max 74ABT TA e b40 C to a 85 C VCC e 4 5V to 5 5V CL e 50 pF Min Max MHz ns ns ns Units 4 Extended AC Electrical Characteristics (SOIC package) 74ABT TA e b40 C to a 85 C VCC e 4 5V to 5 5V CL e 50 pF 8 Outputs Switching (Note 4) Min tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPZL Propagation Delay Dn to On Propagation Delay LE to On Output Enable Time Output Disable Time 15 15 15 15 15 15 10 10 Max 52 52 55 55 62 62 55 55 74ABT TA e b40 C to a 85 C VCC e 4 5V to 5 5V CL e 250 pF (Note 5) Min 20 20 20 20 20 20 (Note 7) Max 68 68 75 75 80 80 74ABT TA e b40 C to a 85 C VCC e 4 5V to 5 5V CL e 250 pF 8 Outputs Switching (Note 6) Min 20 20 20 20 20 20 (Note 7) Max 90 90 95 95 10 5 10 5 ns ns ns ns Symbol Parameter Units Note 4 This specification is guaranteed but not tested The limits apply to propagation delays for all paths described switching in phase (i e all LOW-to-HIGH HIGH-to-LOW etc ) Note 5 This specification is guaranteed but not tested The limits represent propagation delay with 250 pF load capacitors in plce of the 50 pF load capacitors in the standard AC load This specificaiton pertains to single output switching only Note 6 This specification is guaranteed but not tested The limits represent propagation delays for all paths described switching in phase (i e all LOW-to-HIGH HIGH-to-LOW etc ) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load Note 7 The TRI-STATE delay times are dominated by the RC network (500X 250 pF) on the output and has been excluded from the datasheet Skew 74ABT TA e b40 C to a 85 C VCC e 4 5V?5 5V CL e 50 pF 8 Outputs Switching (Note 3) Max tOSHL (Note 1) tOSLH (Note 1) tPS (Note 5) tOST (Note 1) tPV (Note 2) Pin to Pin Skew HL Transitions Pin to Pin Skew LH Transitions Duty Cycle LH?HL Skew Pin to Pin Skew LH HL Transitions Device to Device Skew LH HL Transitions 10 10 14 15 20 74ABT TA e b40 C to a 85 C VCC e 4 5V?5 5V CL e 250 pF 8 Outputs Switching (Note 4) Max 15 15 35 39 40 ns ns ns ns ns Symbol Parameter Units Note 1 Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device The specification applies to any outputs switching HIGH to LOW (tOSHL) LOW to HIGH (tOSLH) or any combination switching LOW to HIGH and or HIGH to LOW (tOST) This specification is guaranteed but not tested Note 2 Propagation delay variation for a given set of conditions (i e temperature and VCC) from device to device This specification is guaranteed but not tested Note 3 This specification is guaranteed but not tested The limits apply to propagation delays for all paths described switching in phase (i e all LOW-to-HIGH HIGH-to-LOW etc ) Note 4 This specification is guaranteed but not tested The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load Note 5 This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin It is measured across all the outputs (drivers) on the same chip the worst (largest delta) number is the guaranteed specification This specification is guaranteed but not tested 5 Capacitance Symbol CIN COUT (Note 1) Parameter Input Capacitance Output Capacitance Typ 5 9 Units pF pF Conditions (TA e 25 C) VCC e 0V VCC e 5 0V Note 1 COUT is measured at frequency f e 1 MHz per MIL-STD-883B Method 3012 tPLH vs Temperature (TA) CL e 50 pF 1 Output Switching Data to Output tPHL vs Temperature (TA) CL e 50 pF 1 Output Switching Data to Output TL F 11547?11 TL F 11547 ? 12 tPZH vs Temperature (TA) CL e 50 pF 1 Output Switching OE to Output tPZL vs Temperature (TA) CL e 50 pF 1 Output Switching OE to Output TL F 11547?13 TL F 11547 ? 14 tPHZ vs Temperature (TA) CL e 50 pF 1 Output Switching OE to Output tPLZ vs Temperature (TA) CL e 50 pF 1 Output Switching OE to Output TL F 11547?15 TL F 11547 ? 16 Dashed lines represent design characteristics for specified guarantees refer to AC Characteristics Tables 6 tSET LOW vs Temperature (TA) CL e 50 pF 1 Output Switching Data to LE tSET HIGH vs Temperature (TA) CL e 50 pF 1 Output Switching Data to LE TL F 11547 ? 17 TL F 11547 ? 18 tHOLD HIGH vs Temperature (TA) CL e 50 pF 1 Output Switching Data to LE tHOLD LOW vs Temperature (TA) CL e 50 pF 1 Output Switching Data to LE TL F 11547 ? 19 TL F 11547 ? 20 tPLH vs Temperature (TA) CL e 50 pF 8 Outputs Switching Data to Output tPHL vs Temperature (TA) CL e 50 pF 8 Outputs Switching Data to Output TL F 11547 ? 21 TL F 11547 ? 22 tPZH vs Temperature (TA) CL e 50 pF 8 Outputs Switching OE to Output tPZL vs Temperature (TA) CL e 50 pF 8 Outputs Switching OE to Output TL F 11547 ? 23 TL F 11547 ? 24 Dashed lines represent design characteristics for specified guarantees refer to AC Characteristics Tables 7 tPHZ vs Temperature (TA) CL e 50 pF 8 Outputs Switching OE to Output tPLZ vs Temperature (TA) CL e 50 pF 8 Outputs Switching OE to Output TL F 11547?25 TL F 11547 ? 26 tPLH vs Load Capacitance TA e 25 C 1 Output Switching Data to Output tPHL vs Load Capacitance TA e 25 C 1 Output Switching Data to Output TL F 11547?27 TL F 11547 ? 28 tPLH vs Load Capacitance TA e 25 C 8 Outputs Switching Data to Output tPHL vs Load Capacitance TA e 25 C 8 Outputs Switching Data to Output TL F 11547?29 TL F 11547 ? 30 tPZH vs Load Capacitance TA e 25 C 8 Outputs Switching OE to Output tPZL vs Load Capacitance TA e 25 C 8 Outputs Switching OE to Output TL F 11547?31 TL F 11547 ? 32 Dashed lines represent design characteristics for specified guarantees refer to AC Characteristics Tables 8 tPLH vs Temperature (TA) CL e 50 pF 1 Output Switching LE to Output tPHL vs Temperature (TA) CL e 50 pF 1 Output Switching LE to Output TL F 11547 ? 35 TL F 11547 ? 36 tPLH vs Temperature (TA) CL e 50 pF 8 Outputs Switching LE to Output tPHL vs Temperature (TA) CL e 50 pF 8 Outputs Switching LE to Output TL F 11547 ? 37 TL F 11547 ? 38 tPLH and tPHL vs Number Outputs Switching CL e 50 pF TA e 25 C VCC e 5 0V Outputs In Phase Data to Output Typical ICC vs Output Switching Frequency CL e 0 pF VCC e VIH e 5 5V LE e GND 1 Output Switching at 50% Duty Cycle Data to Output Transparent Mode with Unused Data Inputs e VIH TL F 11547 ? 33 TL F 11547 ? 34 Dashed lines represent design characteristics for specified guarantees refer to AC Characteristics Tables 9 AC Loading Includes jig and probe capacitance TL F 11547?4 TL F 11547 ? 5 FIGURE 1 Standard AC Test Load FIGURE 4 Propagation Delay Pulse Width Waveforms TL F 11547?6 FIGURE 2a Test Input Signal Levels Amplitude 3 0V Rep Rate 1 MHz tw 500 ns tr 2 5 ns tf 2 5 ns TL F 11547 ? 7 FIGURE 5 TRI-STATE Output HIGH and LOW Enable and Disable Times FIGURE 2b Test Input Signal Requirements TL F 11547 ? 9 TL F 11547?8 FIGURE 3 Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 6 Setup Time Hold Time and Recovery Time Waveforms 10 Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows TL F 11547 ? 39 11 Physical Dimensions inches (millimeters) 20-Terminal Ceramic Chip Carrier (L) NS Package Number E20A 12 Physical Dimensions inches (millimeters) (Continued) 20-Lead Ceramic Dual-In-Line (D) NS Package Number J20A 20-Lead Small Outline Integrated Circuit JEDEC (S) NS Package Number M20B 13 Physical Dimensions inches (millimeters) (Continued) 20-Lead Small Outline Integrated Circuit EIAJ (SJ) NS Package Number M20D 20-Lead Plastic EIAJ SSOP (MSA) NS Package Number MSA20 14 Physical Dimensions inches (millimeters) (Continued) All dimensions are in millimeters 20-Lead Molded Thin Shrink Small Outline Package JEDEC (MTC) NS Package Number MTC20 20-Lead Plastic Dual-In-Line Package (P) NS Package Number N20B 15 54ABT 74ABT373 Octal Transparent Latch with TRI-STATE Outputs Physical Dimensions inches (millimeters) (Continued) 20-Lead Ceramic Flatpak (F) NS Package Number W20A LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications http://www.icinfo.net http://pdf.ecgoo.net

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