54ABT16373W-QML Download

partno	mfr	description	Magnitude	download
54ABT16373W-QML	NSC	National Semiconductor [16-Bit Transparent Latch with TRI-STATE Outputs]	120k

54ABT16373 16-Bit Transparent Latch with TRI-STATE Outputs July 1998 54ABT16373 16-Bit Transparent Latch with TRI-STATE ? Outputs General Description The ABT16373 contains sixteen non-inverting latches with TRI-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is low, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in high Z state. Features n Separate control logic for each byte n 16-bit version of the ABT373 n High impedance glitch free bus loading during entire power up and power down cycle n Non-destructive hot insertion capability n Guaranteed latch-up protection n Standard Microcircuit Drawing (SMD) 5962-9320001 Ordering Code: Military 54ABT16373W-QML Package Number WA48A 48-Lead Cerpack Package Description Logic Symbol Connection Diagram Pin Assignment for Cerpack DS100201-1 Pin Description Pin Names OEn LEn D0?D15 O0?O15 Description Output Enable Input (Active Low) Latch Enable Input Data Inputs Outputs DS100201-2 TRI-STATE ? is a registered trademark of National Semiconductor Corporation. ? 1998 National Semiconductor Corporation DS100201 www.national.com Functional Description The ABT16373 contains sixteen D-type latches with TRI-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the Dn enters the latches. In this condition the latches are transparent, i.e., a latch output will change states each time its D input changes. When LEn is LOW, the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LEn. The TRI-STATE standard outputs are controlled by the Output Enable (OEn) input. When OEn is LOW, the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Truth Tables Inputs LE1 X H H L OE1 H L L L Inputs LE2 X H H L OE2 H L L L D8?D15 X L H X D0?D7 X L H X Outputs O0?O7 Z L H (Previous) Outputs O8?O15 Z L H (Previous) H = High Voltage Level L = Low Voltage Level X = Immaterial Z = High Impedance Previous = previous output prior to HIGH to LOW transition of LE Logic Diagrams DS100201-3 DS100201-4 www.national.com 2 Absolute Maximum Ratings (Note 1) Storage Temperature -65?C to +150?C Ambient Temperature under Bias -55?C to +125?C Junction Temperature under Bias Ceramic -55?C to +175?C VCC Pin Potential to Ground Pin -0.5V to +7.0V Input Voltage (Note 2) -0.5V to +7.0V Input Current (Note 2) -30 mA to +5.0 mA Voltage Applied to Any Output in the Disabled or Power-Off State -0.5V to +5.5V in the HIGH State -0.5V to VCC Current Applied to Output in LOW State (Max) twice the rated IOL (mA) -350 mA DC Latchup Source Current: OE Pin (Across Comm Operating Range) Other Pins Over Voltage Latchup (I/O) -500 mA 10V Recommended Operating Conditions Free Air Ambient Temperature Military Supply Voltage Military Minimum Input Edge Rate Data Input Enable Input -55?C to +125?C +4.5V to +5.5V (V/t) 50 mV/ns 20 mV/ns Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL IIH IBVI IIL VID IOZH IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Input Leakage Test Output Leakage Current Output Leakage Current Output Short-Circuit Current Output High Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input Outputs Enabled Outputs TRI-STATE Outputs TRI-STATE ICCD Dynamic ICC (Note 4) No Load 0.15 -100 4.75 50 -50 -275 50 100 2.0 85 2.0 2.5 2.5 2.5 54ABT 54ABT 54ABT 2.5 2.0 0.55 5 5 7 -5 -5 V ?A ?A mA ?A ?A mA mA mA mA mA mA mA/ MHz Max Max 0.0 0 - 5.5V 0 - 5.5V Max Max 0.0 Max Max Max ?A ?A Max Max V ?A Min Max ABT16373 Min Typ Max 2.0 0.8 -1.2 V V V Min Recognized HIGH Signal Recognized LOW Signal IIN = -18 mA IOH = -3 mA IOH = -24 mA IOL = 48 mA VIN = 2.7V (Note 4) VIN = VCC VIN = 7.0V VIN = 0.5V (Note 4) VIN = 0.0V IID = 1.9 ?A All Other Pins Grounded VOUT = 2.7V; OE = 2.0V VOUT = 0.5V; OE = 2.0V VOUT = 0.0V VOUT = VCC VOUT = 5.5V; All Others GND All Outputs HIGH All Outputs LOW OE = VCC All Others at VCC or GND VI = VCC - 2.1V Enable Input VI = VCC - 2.1V Data Input VI = VCC - 2.1V All Others at VCC or GND Outputs Open, LE = VCC OE = GND, (Note 3) One Bit Toggling, 50% Duty Cycle Note 3: For 8 bits toggling, ICCD < 0.8 mA/MHz. Note 4: Guaranteed, but not tested. Units VCC Conditions 3 www.national.com AC Electrical Characteristics Symbol Parameter 54ABT TA = -55?C to +125?C VCC = 4.5V to 5.5V CL = 50 pF Min tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Propagation Delay Dn to On Propagation Delay LE to On Output Enable Time 1.4 1.4 1.7 1.4 1.1 1.5 1.5 1.6 Max 6.5 6.5 7.0 6.3 6.8 6.8 8.5 8.0 ns ns ns ns Units AC Operating Requirements Symbol Parameter 54ABT TA = -55?C to +125?C VCC = 4.5V to 5.5V CL = 50 pF Min ts(H) ts(L) th(H) th(L) tw(H) Setup Time, HIGH or LOW Dn to LE Hold Time, HIGH or LOW Dn to LE Pulse Width, LE HIGH 2.4 2.4 2.2 2.2 3.3 ns ns Max ns Units Capacitance Symbol CIN COUT (Note 5) Parameter Input Capacitance Output Capacitance Typ 5 11 Units pF pF Conditions (TA = 25?C) VCC = 0V VCC = 5.0V Note 5: COUT is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012. www.national.com 4 AC Loading DS100201-6 *Includes jig and probe capacitance DS100201-11 FIGURE 1. Standard AC Test Load FIGURE 5. Propagation Delay, Pulse Width Waveforms DS100201-7 DS100201-10 FIGURE 2. Test Input Signal Levels FIGURE 6. TRI-STATE Output HIGH and LOW Enable and Disable Times Amplitude 3.0V Rep. Rate 1 MHz tw 500 ns tr 2.5 ns tf 2.5 ns FIGURE 3. Test Input Signal Requirements DS100201-9 FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms DS100201-8 FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions 5 www.national.com 54ABT16373 16-Bit Transparent Latch with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Cerpack NS Package Number WA48A LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Fran?ais Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 www.national.com National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. http://www.icinfo.net http://pdf.ecgoo.net

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partno	mfr	description	Magnitude	download
54ABT16373	NSC	National Semiconductor [16-Bit Transparent Latch with TRI-STATE Outputs]	120k
54ABT16373W-QML	NSC	National Semiconductor [16-Bit Transparent Latch with TRI-STATE Outputs]	120k