0002A01L Download

partno	mfr	description	Magnitude	download
0002A01L	ICST	Integrated Circuit Systems [FEMTOCLOCKS⑩ CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER]	207k

Integrated Circuit Systems, Inc. ICS840002-01 FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER FEATURES ? Two LVCMOS/LVTTL outputs @ 3.3V, 17 typical output impedance ? Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input ? Output frequency range: 56MHz - 175MHz ? VCO range: 560MHz - 700MHz ? Output skew: 12ps (maximum) ? RMS phase jitter at 156.25MHZ (1.875MHz - 20MHz): 0.47ps (typical) Phase noise: Offset Noise Power 100Hz ............... -97.4 dBc/Hz 1kHz .............. -120.2 dBc/Hz 10kHz .............. -127.6 dBc/Hz 100kHz .............. -126.1 dBc/Hz ? Full 3.3V or 3.3V core/2.5V output supply mode ? -30?C to 85?C ambient operating temperature ? Available in both standard and lead-free RoHS compliant packages GENERAL DESCRIPTION The ICS840002-01 is a 2 output LVCMOS/LVTTL Synthesizer optimized to generate Ethernet HiPerClockSTM reference clock frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. Using a 25MHz 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL1:0): 156.25MHz, 125MHz, and 62.5MHz. The ICS840002-01 uses ICS' 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical random rms phase jitter, easily meeting Ethernet jitter requirements. The ICS840002-01 is packaged in a small 16-pin TSSOP package. IC S FREQUENCY SELECT FUNCTION TABLE Inputs F_SEL1 F_SEL0 0 0 1 1 0 1 0 1 M Divider Value 25 25 25 25 N Divider Value 4 5 10 5 Output Frequency (25MHz Ref.) 156.25 125 62.5 125 BLOCK DIAGRAM OE Pullup F_SEL1:0 Pullup:Pullup nPLL_SEL Pulldown nXTAL_SEL XTAL_IN Pulldown 25MHz PIN ASSIGNMENT 2 F_SEL0 nXTAL_SEL TEST_CLK OE MR nPLL_SEL VDDA VDD Q0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 F_SEL1 GND GND Q0 Q1 VDDO XTAL_IN XTAL_OUT OSC XTAL_OUT TEST_CLK Pulldown 0 F_SEL1:0 1 Phase Detector 00 01 10 11 1 VCO 0 N ?4 ?5 ?10 ?5 ICS840002-01 Q1 M = ?25 (fixed) 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View MR 840002AG-01 Pulldown www.icst.com/products/hiperclocks.html REV. B JANUARY 13, 2006 1 Integrated Circuit Systems, Inc. ICS840002-01 FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER Type Input Input Input Input Input Pullup Pulldown Pulldown Pullup Pulldown Description Frequency select pin. LVCMOS/LVTTL interface levels. Selects between the cr ystal or TEST_CLK inputs as the PLL reference source. When HIGH, selects TEST_CLK. When LOW, selects XTAL inputs. LVCMOS/LVTTL interface levels. Single-ended LVCMOS/LVTTL clock input. Output enable pin. When HIGH, the outputs are active. When LOW, the outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing active outputs to go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. PLL Bypass. When LOW, the output is driven from the VCO output. When HIGH, the PLL is bypassed and the output frequency = reference clock frequency/N output divider. LVCMOS/LVTTL interface levels. Analog supply pin. Core supply pin. Cr ystal oscillator interface. XTAL_OUT is the output. XTAL_IN is the input. Output supply pin. Single-ended clock outputs. LVCMOS/LVTTL interface levels. Power supply ground. Pullup Frequency select pin. LVCMOS/LVTTL interface levels. TABLE 1. PIN DESCRIPTIONS Number 1 2 3 4 5 Name F_SEL0 nXTAL_SEL TEST_CLK OE MR 6 7 8 9, 10 11 12, 13 14, 15 16 nPLL_SEL VDDA VDD XTAL_OUT, XTAL_IN VDDO Q1, Q0 GND F_SEL1 Input Power Power Input Power Output Power Input Pulldown NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance Input Pullup Resistor Input Pulldown Resistor Output Impedance 3.3V?5% 2.5V?5% 14 16 Test Conditions Minimum Typical 4 8 51 51 17 21 21 25 Maximum Units pF pF k k 840002AG-01 www.icst.com/products/hiperclocks.html 2 REV. B JANUARY 13, 2006 Integrated Circuit Systems, Inc. ICS840002-01 FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER 4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 89?C/W (0 lfpm) -65?C to 150?C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V?5%, VDDO = 3.3V?5% OR 2.5V?5%, TA = 0?C TO 70?C Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 2.375 Typical 3.3 3.3 3.3 2.5 Maximum 3.465 3.465 3.465 2.625 100 12 5 Units V V V V mA mA mA TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V?5%, VDDO = 3.3V?5% OR 2.5V?5%, TA = -30?C TO 85?C Symbol Parameter VIH VIL IIH Input High Voltage Input Low Voltage Input High Current OE, F_SEL0, F_SEL1 nPLL_SEL, MR, nXTAL_SEL, TEST_CLK OE, F_SEL0, F_SEL1 IIL Input Low Current nPLL_SEL, MR, nXTAL_SEL, TEST_CLK VDD = VIN = 3.465V or 2.625V VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V VDD = 3.465V or 2.625V, VIN = 0V VDDO = 3.465V?5% VDDO = 2.5V?5% VDDO = 3.3V or 2.5V?5% Test Conditions Minimum Typical 2 -0.3 Maximum VDD + 0.3 0.8 5 150 -150 -5 2.6 1.8 0.5 Units V V ?A ?A ?A ?A V V V VOH VOL Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information, Output Load Test Circuits. 840002AG-01 www.icst.com/products/hiperclocks.html REV. B JANUARY 13, 2006 3 Integrated Circuit Systems, Inc. ICS840002-01 FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER Test Conditions Minimum Typical 25 50 7 1 Maximum Units MHz pF mW TABLE 4. CRYSTAL CHARACTERISTICS Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant cr ystal. Fundamental TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V?5%, TA = -30?C TO 85?C Symbol fOUT t sk(o) t jit(?) tR / tF Parameter Output Frequency Output Skew; NOTE 1, 3 156.25MHz (1.875MHz - 20MHz) RMS Phase Jitter (Random); NOTE 2 Output Rise/Fall Time 125MHz (1.875MHz - 20MHz) 62.5MHz (1.875MHz - 20MHz) 20% to 80% 200 0.47 0.57 0.51 700 54 Test Conditions F_SEL[1:0] = 00 F_SEL[1:0] = 01 F_SEL[1:0] = 10 or 11 Minimum 14 0 112 56 Typical Maximum 175 140 70 12 Units MHz MHz MHz ps ps ps ps ps % odc Output Duty Cycle 46 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V?5%, VDDO = 2.5V?5%, TA = -30?C TO 85?C Symbol fOUT t sk(o) t jit(?) tR / tF Parameter Output Frequency Output Skew; NOTE 1, 3 156.25MHz (1.875MHz - 20MHz) RMS Phase Jitter (Random); NOTE 2 Output Rise/Fall Time 125MHz (1.875MHz - 20MHz) 62.5MHz (1.875MHz - 20MHz) 20% to 80% 200 0.47 0.55 0.49 700 54 Test Conditions F_SEL[1:0] = 00 F_SEL[1:0] = 01 F_SEL[1:0] = 10 or 11 Minimum 140 112 56 Typical Maximum 175 140 68 12 Units MHz MHz MHz ps ps ps ps ps % odc Output Duty Cycle 46 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 840002AG-01 www.icst.com/products/hiperclocks.html 4 REV. B JANUARY 13, 2006 Integrated Circuit Systems, Inc. ICS840002-01 FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE AT 62.5MHZ @3.3V 0 -10 -20 -30 -40 -50 1Gb Ethernet Filter 62.5MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.51ps (typical) NOISE POWER dBc Hz -60 -70 -80 -90 -100 Raw Phase Noise Data -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k Phase Noise Result by adding 1Gb Ethernet Filter to raw data 1M 10M 100M 100k OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 156.25MHZ @3.3V 0 -20 -30 -40 -50 10Gb Ethernet Filter 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.47ps (typical) -10 NOISE POWER dBc Hz -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -170 -180 -190 100 1k 10k 100k -160 Raw Phase Noise Data Phase Noise Result by adding 10Gb Ethernet Filter to raw data 1M 10M 100M REV. B JANUARY 13, 2006 OFFSET FREQUENCY (HZ) 840002AG-01 www.icst.com/products/hiperclocks.html 5 Integrated Circuit Systems, Inc. ICS840002-01 FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 1.65V?5% 2.05V?5% 1.25V?5% VDD, VDDA, VDDO SCOPE Qx VDD, VDDA SCOPE VDDO GND Qx LVCMOS GND LVCMOS -1.65V?5% -1.25V?5% 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT Phase Noise Plot Noise Power V Qx DDO 2 Phase Noise Mask V Qy DDO 2 tsk(o) f1 Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot RMS PHASE JITTER OUTPUT SKEW V 80% 20% tR 80% Q0, Q1 DDO 2 Clock Outputs 20% tF t PW t PERIOD odc = t PW t PERIOD x 100% OUTPUT RISE/FALL TIME 840002AG-01 OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD www.icst.com/products/hiperclocks.html 6 REV. B JANUARY 13, 2006 Integrated Circuit Systems, Inc. ICS840002-01 FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS840002-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10?F and a .01F bypass capacitor should be connected to each VDDA. The 10 resistor can also be replaced by a ferrite bead. 3.3V VDD .01F VDDA .01F 10F 10 FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE The ICS840002-01 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error. XTAL_IN C1 22p X1 18pF Parallel Cry stal XTAL_OUT C2 22p ICS84332 ICS840002-01 Figure 2. CRYSTAL INPUt INTERFACE 840002AG-01 www.icst.com/products/hiperclocks.html REV. B JANUARY 13, 2006 7 Integrated Circuit Systems, Inc. ICS840002-01 FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. TEST_CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the TEST_CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached. LAYOUT GUIDELINE Figure 3 shows a schematic example of the ICS840002-01. An example of LVCMOS termination is shown in this schematic. Additional LVCMOS termination approaches are shown in the LVCMOS Termination Application Note. In this example, an 18 pF parallel resonant 25MHz crystal is used. The C1=22pF and Logic Control Input Examples VDD C2=22pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. 1K pullup or pulldown resistors can be used for the logic control input pins. Set Logic Input to '1' RU1 1K VDD Set Logic Input to '0' RU2 Not Install VDD R2 33 Zo = 50 Ohm To Logic Input pins RD1 Not Install RD2 1K To Logic Input pins U1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Zo = 50 Ohm C5 0.1u XTAL2 R4 100 LVCMOS VDD R1 10 VDDA C3 10uF C4 0.01u C6 0.1u FSEL0 XTAL_SEL TEST_CLK OE MR nPLL_SEL VDDA VDD FSEL1 GND GND Q0 Q1 VDDO XTAL_IN XTAL_OUT VDD R3 100 ICS840002-01 If not using the crystal input, it can be left floating. For additional protection the XTAL_IN pin can be tied to ground. LVCMOS C2 22pF X1 XTAL1 Optional Termination C1 22pF Unused output can be left floating. There should no trace attached to unused output. Device characterized with all outputs terminated. FIGURE 3. ICS840002-01 SCHEMATIC EXAMPLE 840002AG-01 www.icst.com/products/hiperclocks.html 8 REV. B JANUARY 13, 2006 Integrated Circuit Systems, Inc. ICS840002-01 FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 6. JAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP JA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1?C/W 89.0?C/W 200 118.2?C/W 81.8?C/W 500 106.8?C/W 78.1?C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS840002-01 is: 3085 840002AG-01 www.icst.com/products/hiperclocks.html REV. B JANUARY 13, 2006 9 Integrated Circuit Systems, Inc. ICS840002-01 FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER 16 LEAD TSSOP PACKAGE OUTLINE - G SUFFIX FOR TABLE 7. PACKAGE DIMENSIONS SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0? -4.30 -0.05 0.80 0.19 0.09 4.90 6.40 BASIC 4.50 0.65 BASIC 0.75 8? 0.10 Millimeters Minimum 16 1.20 0.15 1.05 0.30 0.20 5.10 Maximum Reference Document: JEDEC Publication 95, MO-153 840002AG-01 www.icst.com/products/hiperclocks.html 10 REV. B JANUARY 13, 2006 Integrated Circuit Systems, Inc. ICS840002-01 FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS840002AG-01 40002A01 16 Lead TSSOP tube -30?C to 85?C ICS840002AG-01T 40002A01 16 Lead TSSOP 2500 tape & reel -30?C to 85?C ICS840002AG-01LF 0002A01L 16 Lead "Lead-Free" TSSOP tube -30?C to 85?C ICS840002AG-01LFT 0002A01L 16 Lead "Lead-Free" TSSOP 2500 tape & reel -30?C to 85?C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 840002AG-01 www.icst.com/products/hiperclocks.html REV. B JANUARY 13, 2006 11 Integrated Circuit Systems, Inc. ICS840002-01 FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER REVISION HISTORY SHEET Rev Table Page 1 4 8 11 B T4 T8 Description of Change Features Section - corrected the integration range from 1.875MHz - 175MHz to 1.875MHz - 20MHz in the RMS phase jitter bullet. Cr ystal Characteristics Table - added Drive Level. Added Recommendations for Unused Input and Output Pins. Ordering Information Table - corrected standard marking and added Lead-Free par t number, marking and note. Date 1/13/06 840002AG-01 www.icst.com/products/hiperclocks.html 12 REV. B JANUARY 13, 2006 http://www.icinfo.net http://pdf.ecgoo.net

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